Regviz

Espressif Systems /ESP32-S3 /I2C0 /FIFO_ST

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as FIFO_ST

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-S3/I2C0/FIFO_ST#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RXFIFO_RADDR 0RXFIFO_WADDR 0TXFIFO_RADDR 0TXFIFO_WADDR 0SLAVE_RW_POINT

Description

FIFO status register.

Fields

RXFIFO_RADDR

This is the offset address of the APB reading from rxfifo
RXFIFO_WADDR

This is the offset address of i2c module receiving data and writing to rxfifo.
TXFIFO_RADDR

This is the offset address of i2c module reading from txfifo.
TXFIFO_WADDR

This is the offset address of APB bus writing to txfifo.
SLAVE_RW_POINT

The received data in I2C slave mode.

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data